FPGA Designer Training

Day 1

Topic 1: Introduction to FPGA

• Cyclone/Stratix device Architecture
• Introduction to Quartus II
• Creating Project 
• Using Editor & Design Entry

Topic 2: Analysis and Elaboration

• I/O Assignment
• Configure voltage for I/0
• I/O Assignment Analysis
• Synthesis
• Netlist Viewer

Topic 3: Constraints

• Importance of Constraints in Design 
• Clock frequency
• Asynchronous & Synchronous Design
• False Path/Multicycle path

Day 2

Topic 4: Debugging Tools

• Power Analysis 
• SignalTap II embedded logic analyzer
• JTAG Chain Debug Tool
• In-System Memory Content Editor

Topic 5: Placing Design in FPGA

• Fitter (Place & Route)
• Chip Planner
• Assembler (Generating Programming file)
• Downloading Design in FPGA

Topic 6: Static Time analysis (STA)

• Running TimeQuest Timing Analyzer
• Understanding reports 
• Understand setup/hold violation & failing paths
• Constraining and understanding TCL Commands

Promotion Code

Your will get 10% discount voucher for 2nd course onwards if you write us a Google review.

Minimum Entry Requirement

Knowledge and Skills

• Able to operate using computer functions
• Minimum 3 GCE ‘O’ Levels Passes including English or WPL Level 5 (Average of Reading, Listening, Speaking & Writing Scores)

Attitude

• Positive Learning Attitude
• Enthusiastic Learner

Experience

• Minimum of 1 year of working experience.

Target Age Group: 18-65 years old

Minimum Software/Hardware Requirement

Software:

TBD

Hardware: Window or Mac Laptops

• Digital IC Aesigners
• VHDL/VERILOG Arogrammers
• FPGA Architects
• Embedded design Engineers

Dr. Florence Choong: Dr. Florence Choong received the BEng. (First class) from Multimedia University, Malaysia in 2002. She then completed her Masters of Engineering Science (MEngSc) degree in Multimedia University, Cyberjaya in 2005 and PhD in Engineering in 2012. Recently, she has completed her Masters in Business Administration (MBA) from the University of Derby, UK.

Upon graduation, she started her career in the telecommunications and networking industry where she served TM for three years in various departments such as networking, IT, quality assurance and customer service. Being passionate in research and training and educating the youth, she then moved to the academic and research line where she joined Multimedia University (MMU) as a lecturer in 2005. She then moved on to University Tunku Abdul Rahman (UTAR) in 2008 as a senior lecturer. She was the Head of the Electrical and Electronics Engineering department in Taylor’s University leading the programme to its first accreditation. At present, she is senior lecturer and is also very active in research. She has a total of more than 10 years of teaching experience. She is also a Chartered Engineer and is registered with the Board of Engineers Malaysia (BEM) and IEM. She is also the advisor to the Taylors IET On Campus.

She is author and co-author of numerous international journal and conference papers published by renowned journals in power quality, VLSI system design and artificial intelligence. Her current research interests are in the area of artificial intelligence, digital and VLSI design. She has also extended her skills and knowledge in this area through various consultancy works.