Verilog Programming Training for FPGA

Day 1

FPGA Design FLOW

• Motivation

Topic 1 : Architecture of FPGA

• Introduction to Programmable logic device (PLD)
• Architecture
• Structure of PLD

Topic 2 : Introduction to Verilog

• Levels of Abstraction
• Syntax & Semantics
• Reserved Keywords

Topic 3: Verilog Ports

• Ports declaration
• Data types
• Physical
• Abstract
• Constant

Topic 4: Operators

• Arithmetic Operator
• Bit Wise
• Logical
• Reduction
• Shift
• Relational/Equality/Concatenation/Replication/Conditional

Topic 5: Modeling

• Data Flow
• Behavioral
• Structural

Topic 6: Timing Control

• Inertia Delay
• Transport Delay
• Event Control
• Back-Annotation

Topic 7 : Conditional statement

• if
• Nested if
• Case, casex, casez

Topic 8: User Define Primitives.

• Process statement / Sensitivity List

Topic 9: Lab Exercise

• Combinational Logic

Day 2

Topic 10: State Machine

• Mealy 
• Moore

Topic 11: Simulation

• Steps of simulation / Simulation Deltas
• Test bench

Topic 13: Lab Activities

• Design Entry
• Writing Verilog code 
• Test bench 
• Simulating Verilog code with Vivado (Xilinx)
• Synthesize the code

Promotion Code

Your will get 10% discount voucher for 2nd course onwards if you write us a Google review.

Minimum Entry Requirement

Knowledge and Skills

• Able to operate using computer functions
• Minimum 3 GCE ‘O’ Levels Passes including English or WPL Level 5 (Average of Reading, Listening, Speaking & Writing Scores)

Attitude

• Positive Learning Attitude
• Enthusiastic Learner

Experience

• Minimum of 1 year of working experience.

Target Age Group: 18-65 years old

Minimum Software/Hardware Requirement

Software:

• Vivado Design Suite https://www.xilinx.com/support/download.html

Hardware: Window or Mac Laptops

• Digital IC Designers
• VHDL/VERILOG Programmers
• FPGA Architects
• Embedded Design Engineers

Dr. Florence Choong: Dr. Florence Choong received the BEng. (First class) from Multimedia University, Malaysia in 2002. She then completed her Masters of Engineering Science (MEngSc) degree in Multimedia University, Cyberjaya in 2005 and PhD in Engineering in 2012. Recently, she has completed her Masters in Business Administration (MBA) from the University of Derby, UK.

Upon graduation, she started her career in the telecommunications and networking industry where she served TM for three years in various departments such as networking, IT, quality assurance and customer service. Being passionate in research and training and educating the youth, she then moved to the academic and research line where she joined Multimedia University (MMU) as a lecturer in 2005. She then moved on to University Tunku Abdul Rahman (UTAR) in 2008 as a senior lecturer. She was the Head of the Electrical and Electronics Engineering department in Taylor’s University leading the programme to its first accreditation. At present, she is senior lecturer and is also very active in research. She has a total of more than 10 years of teaching experience. She is also a Chartered Engineer and is registered with the Board of Engineers Malaysia (BEM) and IEM. She is also the advisor to the Taylors IET On Campus.

She is author and co-author of numerous international journal and conference papers published by renowned journals in power quality, VLSI system design and artificial intelligence. Her current research interests are in the area of artificial intelligence, digital and VLSI design. She has also extended her skills and knowledge in this area through various consultancy works.